Job description
Minimum qualifications:
- Master’s degree in Electrical Engineering, Computer Science or equivalent practical experience.
- 10 years of experience in ASIC design implementation flows.
- Experience in driving execution for low-power physical design implementation with industry standard synthesis, PnR, and Static Timing Analysis (STA) tools.
- Experience in sign-off convergence including STA, electrical checks, and physical verification.
Preferred qualifications:
- 5 years of experience on high-performance CPUs and leading processor Physical Design teams.
- Experience in CPU implementation, including but not limited to critical timing and power fix iterations with RTL and Micro architecture teams.
- Experience in delivering dynamic metric driven Performance Power Area (PPA) goals.
- Experience in programming and scripting languages such as Python, TCL, or Perl.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Pulling on your technical and leadership expertise, you lead end-to-end research projects in multiple areas of expertise across data center facilities and manage a team of direct reports working on equipment installation, troubleshooting and debugging.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $172,000-$263,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Drive industry leading high-performance and low power complex design implementation for advanced CPUs.
- Manage block and hierarchical physical implementation and Quality of Results (QoR) (e.g., power, timing, area).
- Collaborate with RTL design, cross-site Physical Design and CAD teams on micro architectural critical items for timing and power convergence.
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